This application is based upon and claims priority of Japanese Patent Application No. 2000-198099, filed on Jun. 30, 2000, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and methods for controlling activation thereof, in particular, suitable for use in a redundancy judgment circuit for determining redundancy of a redundant circuit upon activation.
2. Description of the Related Art
In order to lower electric power consumption, conventionally, an integrated circuit of a memory or the like has been required to lower the operational voltage. In recent years, for example, in a DRAM (Dynamic Random Access Memory), there is an integrated circuit that operates with an inner power supply voltage of about 2.0 V and a negative voltage of about xe2x88x920.5 V.
A redundant circuit has been provided in the integrated circuit of a memory or the like in advance to remedy failure due to defect in the integrated circuit. In the case that failure has occurred in a portion of the circuit, the circuit that the failure occurs has been replaced with a redundant circuit to remedy the failure. In this integrated circuit provided with the redundant circuit, a fuse or the like to select whether the redundant circuit should be used or not is disposed and to replace the circuit, in which failure has occurred, with the redundant circuit is selected depending on whether the fuse or the like should be cut or not. In this case, when the integrated circuit is used in a normal operation, it is judged by a redundancy judgment circuit upon activation whether the integrated circuit lies in the condition of using the redundant circuit or not.
FIG. 1 is a diagram for showing a constitutional example of a redundancy judgment circuit, which is used in a conventional memory or the like.
In FIG. 1, a reference numeral 1 denotes a starter signal generation circuit for generating and outputting a starter signal STT in order to determine an initial state of a peripheral circuit. This starter signal STT rises together with a power supply voltage Vii when the power supply is turned on and it is reset at a low level when the potential of the power supply voltage Vii reaches a predetermined potential Vb.
A reference numeral 2xe2x80x2 denotes a negative voltage generation circuit, which generates a negative voltage Vnn to be used in the integrated circuit including the redundancy judgment circuit. The negative voltage Vnn generated by the negative voltage generation circuit 2xe2x80x2 is supplied to a starter signal level shifter 3, a fuse set pulse generation circuit 4 and a fuse information latch circuit 5 or the like.
The starter signal level shifter 3 shifts a low level of the starter signal STT, which is supplied from the starter signal generation circuit 1, from a ground potential Vss to a potential of the negative voltage Vnn. The starter signal level shifter 3 supplies a signal, which shows that the low level is shifted to the potential of the negative voltage Vnn, to the fuse set pulse generation circuit 4 and the fuse information latch circuit 5 as a fuse starter signal STTB.
The fuse set pulse generation circuit 4 comprises a circuit for generating a fuse set pulse signal FSETP to judge the redundancy on the basis of the supplied fuse starter signal STTB. Then, the fuse set pulse generation circuit 4 supplies the generated fuse set pulse signal FSETP to the fuse information latch circuit 5.
The fuse information latch circuit 5 is provided with a fuse to select whether the redundant circuit should be used or not. The fuse information latch circuit 5 judges upon activation whether the fuse is cut or not and stores this judgment result therein. That is, the fuse information latch circuit 5 uses the generated fuse set pulse signal FSETP, which is supplied from the fuse set pulse generation circuit 4, to judge upon activation whether the current fuse is cut or not and store this judgment result therein. The fuse information latch circuit 5 outputs the above judgment result through an output node 6 as an output signal FSZ.
The low level of each of the fuse set pulse signal FSETP and the output signal FSZ respectively output from the above described fuse set pulse generation circuit 4 and the above described fuse information latch circuit 5 is equal to the potential of the negative voltage Vnn.
FIG. 2 is a diagram for showing a configuration of a conventional negative voltage generation circuit 2xe2x80x2.
In FIG. 2, a reference numeral 31 denotes a negative voltage judgment circuit. The negative voltage judgment circuit 31 judges whether the potential of the negative voltage Vnn to be output through an output node 34 of the negative voltage generation circuit 2xe2x80x2 is lowered to a predetermined potential or not. Additionally, the negative voltage judgment circuit 31 outputs the judgment result to a negative voltage generation enable circuit 32.
The negative voltage generation enable circuit 32 outputs an enable signal EN for controlling a negative voltage generation operation. This enable signal EN is generated on the basis of the judgment result to be supplied from the negative voltage judgment circuit 31 and a memory bank activation signal BRAS to be input through an input node 35. Additionally, the memory bank activation signal BRAS comprises a signal such that xe2x80x98Hxe2x80x99 is output upon activating the memory bank. However, it is clamped in xe2x80x98Lxe2x80x99 by a not-shown circuit upon activation. Therefore, the negative voltage generation enable circuit 32 outputs the enable signal EN only on the basis of the judgment result to be supplied from the negative voltage judgment circuit 31 upon activation.
A reference numeral 33 denotes an oscillation and pumping circuit. The oscillation and pumping circuit 33 generates the negative voltage Vnn and outputs it through the output node 34 in accordance with the enable signal EN to be supplied from the negative voltage generation enable circuit 32. The oscillation and pumping circuit 33 shown in FIG. 2 performs the negative voltage generation operation when the enable signal EN is xe2x80x98Hxe2x80x99 and it does not perform the negative voltage generation operation when the enable signal EN is xe2x80x98Lxe2x80x99.
FIG. 3 is a timing chart for explaining the operation of a conventional redundancy judgment circuit.
In FIG. 3, the power supply voltage Vii rises up when the power supply is turned on at a time of T10. As the power supply voltage Vii rises up, the enable signal EN, the starter signal STT, the fuse starter signal STTB, the fuse set pulse signal FSETP and the output signal FSZ also rise up.
When the potential of the power supply voltage Vii reaches a predetermined potential Va at a time of T11, the oscillation and pumping circuit 33 in the negative voltage generation circuit 2xe2x80x2 detects that the enable signal EN is xe2x80x98Hxe2x80x99. This allows the negative voltage generation operation to be started by the oscillation and pumping circuit 33 and the potential of the negative voltage Vnn to be output from the negative voltage generation circuit 2xe2x80x2 is lowered. Then, the oscillation and pumping circuit 33 continues the negative voltage generation operation until a time of T12, when the potential of the negative voltage Vnn reaches a predetermined potential.
When the negative voltage judgment circuit 31 judges that the potential of the negative voltage Vnn reaches a predetermined potential at a time of T12, the negative voltage judgment circuit 31 outputs this judgment result to the negative voltage generation enable circuit 32. Depending on this judgment result, the negative voltage generation enable circuit 32 makes the enable signal EN at xe2x80x98Lxe2x80x99. Thus, the negative voltage generation operation of the oscillation and pumping circuit 33 is not performed and the negative voltage Vnn to be output from the negative voltage generation circuit 2xe2x80x2 becomes a predetermined voltage.
Further, as the power supply voltage Vii rises up and the power supply voltage Vii reaches a predetermined potential Vb at a time of T13, the, starter signal STT is reset to xe2x80x98Lxe2x80x99. In accordance with this, the fuse starter signal STTB to be output from the starter signal level shifter 3 becomes xe2x80x98Lxe2x80x99. Thus, the fuse set pulse signal FSETP is generated by the fuse set pulse generation circuit 4.
Then, this fuse set pulse signal FSETP is supplied to the fuse information latch circuit 5 and the redundancy of the redundant circuit is judged, so that the judgment result is latched. After this, the fuse information latch circuit 5 continues to hold the judgment result. As a result of the judgment of the redundancy, the fuse information latch circuit 5 makes the output signal FSZ at xe2x80x98Lxe2x80x99 in the case that the redundant circuit is not redundant, namely, the redundant circuit is used and it keeps the output signal FSZ in xe2x80x98Hxe2x80x99 in the case that the redundant circuit is redundant.
The potential of the power supply voltage Vii becomes constant at a time of T14. After that, if the potential of the negative voltage Vnn is higher than a predetermined potential, for example, at a time of T15, it is judged by the negative voltage judgment circuit 31 that the potential of the negative voltage Vnn is higher than a predetermined potential. Then, this judgment result is input in the negative voltage generation enable circuit 32 and the enable signal EN to be output from the negative voltage generation enable circuit 32 becomes xe2x80x98Hxe2x80x99. Thus, the negative voltage generation operation is commences again by the oscillation and pumping circuit 33.
In this case, if the potential of the negative voltage Vnn is lower than a predetermined potential at a time of T16, it is judged by the negative voltage judgment circuit 31 that the potential of the negative voltage Vnn is lower than a predetermined potential. In accordance with this, the negative voltage generation enable circuit 32 makes the enable signal EN at xe2x80x98Lxe2x80x99. Thus, the oscillation and pumping circuit 33 does not perform the negative voltage generation operation and the potential of the negative voltage Vnn becomes constant.
As described above, the redundancy judgment circuit shown in FIG. 1 performs the redundancy judgment of the redundant circuit.
The low level of the fuse starter signal STTB to be supplied to the fuse information latch circuit 5 is defined as a potential of a negative voltage Vnn in the redundancy judgment circuit shown in FIG. 1. This intends to prevent a feedthrough current from being generated in the redundant circuit after resetting (at and after the time of T13 in FIG. 3) in the case that the above described redundancy judgment circuit is used as a redundancy judgment circuit of a word line of a memory or the like. That is, if the low level of the fuse starter signal STTB is not defined as a potential of a negative voltage Vnn but defined as a ground potential Vss, the feedthrough current may be generated after resetting, since the low level of the fuse starter signal STTB is higher than the negative voltage Vnn as a reset voltage of the word line.
Thus, the redundancy judgment circuit shown in FIG. 1 shifts the low level of the starter signal STT (a ground potential Vss) to the potential of the negative voltage Vnn by the starter signal level shifter 3. Then, the redundancy judgment circuit outputs the shifted low level as the fuse starter signal STTB.
However, in associated with lowering of the voltage of the power supply, the voltage of the power supply and the operational voltage of the integrated circuit are not always capable of being lowered at the same ratio. For example, it is not possible to lower the negative voltage in a reset potential of a word line of a memory or the like at the same ratio as that of the power supply in order to control leakage upon standby. In this case, the high level is relatively lowered. Therefore, in the case that the signal is changed from the high level to the low level or the like, it becomes difficult to shift the low level from the ground potential to the negative potential.
In order to solve this problem, there is a method to adjust size of a transistor so that the level shift becomes easy in the case that the level shifter for level shift is configured of a transistor.
However, according to the method to adjust the size of the transistor, there is a limitation in the range capable of being made smaller in the case of decreasing the size of the transistor. Therefore, this involves such a problem that other transistors should be made larger. Further, in the case that the voltage of the power supply is lowered, so that, for example, the voltage of the power supply becomes 0.8 V and the negative voltage becomes about xe2x88x920.5 V, there is such a problem that the level shift is difficult only by adjusting the size of the transistor.
Besides, in the case that a noise is loaded on a signal to be input in the level shifter, the conventional level shifter involves such a problem that it faithfully level-shifts and outputs the signal which is loaded with the noise.
The present invention has been made taking the foregoing problems into consideration, an object of which is to enable to easily shift the low level without increasing the size of the transistor even when the voltage of the power supply is lowered.
Additionally, the second object of the present invention is to make a noise difficult to be transmitted to an output signal even when the signal loaded with the noise is input and make the signal strong to the noise.
A semiconductor integrated circuit according to the present invention is characterized in that the semiconductor integrated circuit comprises a voltage generation circuit, which rises up together with a power supply voltage to be supplied after a power supply is turned on, does not perform a voltage generation operation before the predetermined information is latched by a latch circuit on the basis of an input signal, which becomes a low level when the power supply voltage reaches a predetermined potential or its complementary signal and performs the voltage generation operation after the predetermined information is latched by the latch circuit.
Further, a semiconductor integrated circuit according to the present invention is characterized in that the semiconductor integrated circuit comprises a voltage generation circuit described as below. That is, on the basis of an input signal, of which level is shifted from a first potential to a second potential which is lower than the first potential, the voltage generation circuit generates higher potential than a finally attained potential as a second potential before the predetermined information is latched by the latch circuit, and generates the finally attained potential as the second potential after the predetermined information is latched by the latch circuit.
Additionally, a method for controlling activation according to the present invention is. characterized in that the method comprises supplying a potential, which is not more than a ground potential and is higher than the finally attained potential, to the latch circuit as a negative potential and shifting a low level of an input signal to be input from the ground potential to the negative potential to output it and supplying the finally attained potential as the negative potential after the predetermined information is latched to the latch circuit on the basis of the output signal.
According to the present invention constituted as described above, the predetermined information is latched to a latch circuit on the basis of the input signal, of which low level is shifted from a first potential to a potential that is higher than a potential to which the low level will be finally reach. Then, after the latch circuit latches the predetermined information, the low level is made into a finally attained potential. That is, the low level has been shifted to a potential that is higher than a finally attained potential until the predetermined information is latched to the latch circuit. Thus, the potential difference to be shifted is smaller compared with a case that the low level is shifted to the finally attained potential. Since the low levels of the level shift circuit and the latch circuit become the finally attained potential after that, it becomes easy to shift the low level without increasing the size of the transistor even when the power supply voltage is lowered.
Besides, the low level has been shifted to a potential that is higher than a finally attained potential until the predetermined information is latched to the latch circuit. After the predetermined information is latched to the latch circuit, a voltage generated by the voltage generation circuit is supplied and the low level becomes the finally attained potential. On this account, after the predetermined information is latched to the latch circuit, it becomes difficult to invert a signal, so that a noise is hardly transmitted to an input signal even when the noise is loaded on the input signal and the predetermined information in the latch circuit is made strong to disturbance.